fix storage builtins

diff --git a/rel-lang/sorelc/src/riscv_asm_codegen.rs b/rel-lang/sorelc/src/riscv_asm_codegen.rs
index 5caeffd642c350284f73f51066c3c5f606c4b7f5..c382cdfc3e8114e5b75e47cc2672f245825741c1 100644 (file)
--- a/rel-lang/sorelc/src/riscv_asm_codegen.rs
+++ b/rel-lang/sorelc/src/riscv_asm_codegen.rs
@@ -199,15 +199,15 @@ impl<'a> CodeGen<'a> {
                 },
                 IR::Store8 => { // ( x addr -- )
                     self.pop_some_to("t0 t1");
-                    self.line("sbu t0, 0(t1)"); // store x at addr 
+                    self.line("sb t0, 0(t1)"); // store x at addr 
                 },
                 IR::Store16 => { // ( x addr -- )
                     self.pop_some_to("t0 t1");
-                    self.line("shu t0, 0(t1)"); // store x at addr 
+                    self.line("sh t0, 0(t1)"); // store x at addr 
                 },
                 IR::Store32 => { // ( x addr -- )
                     self.pop_some_to("t0 t1");
-                    self.line("shu t0, 0(t1)"); // store x at addr 
+                    self.line("sw t0, 0(t1)"); // store x at addr 
                 },
                 IR::Store => { // ( x addr -- )
                     self.pop_some_to("t0 t1");